1. Field of the Invention
The present invention generally relates to a semiconductor memory device such as a semiconductor memory with a large scale integration according to the recent trend. More particularly, the present invention relates to a semiconductor memory device provided with a so-called redundancy circuit for replacing a defective memory cell by a spare memory cell.
2. Description of the Prior Art
A conventional semiconductor memory device having a redundancy circuit comprises, as shown in FIG. 4, a memory 1, a spare memory 2, a relief address memory 6 as a circuit for storing defective addresses, a spare row or column instruction memory 7 as a circuit for storing spare rows or spare columns, and a spare row or column decoder 4 as a control circuit for enabling a spare memory cell and disabling a regular memory cell. When a defective memory cell exists in the memory 1, the above stated semiconductor memory device replaces the row or the column containing the defective memory cell by a spare row or column in the spare memory 2 so that a memory cell in good condition can be used instead. Thus, the operation efficiency can be considerably improved.
In the future, according to further development of fine patterning technology, a redundancy circuit will become a more indispensable technique for the purpose of reducing the manufacturing cost of a large-capacity memory. On such occasion, it is important to utilize information as to whether each memory chip uses a spare row or column. In addition, in order to obtain a high yield of manufacturing, it is necessary to feed back to the manufacturing process the information as to the cause by which a memory cell in the memory portion 1 is defective. Information as to defectiveness in bits due to a defective patterning of a contact opening, defectiveness in lines due to rupture or short circuit of the connection of aluminum or polysilicon or the like is very useful for establishing the optimum conditions in the manufacturing process. However, such a conventional redundancy circuit system involves disadvantages that once a regular memory portion has been replaced by a redundancy circuit portion, it can not be determined from the outside whether the redundancy circuit is in use or not, or a defective memory cell can not be identified even if the state of the redundancy circuit can be determined. Moreover, in order to fetch to the exterior the address of the defective memory cell relieved by the redundancy circuit, a special circuit is required to perform special reading operation.